As semiconductor fabrication processes pack more circuitry into smaller packages, integrated circuit (IC) designs are becoming more three-dimensional (3D). It is difficult to measure, analyze and locate faults in 3D microscopic (including nanoscopic) structures.
An engineer will typically identify a region-of-interest (ROI) that he wants to investigate, based upon, for example, aberrant electrical behavior of a circuit component. Most ROIs in conventional ICs are confined to a small volume of the device in a planar region. For example, a static random access memory (SRAM) or a conventional “not-and” (NAND) flash cell each occupies a distinct X and Y location, with a small volume of active area in the Z direction. An engineer typically identifies the ROI by starting with a logic bit or gate address, which can then be mapped to a physical X/Y location in an active region of the structure.
The ROI is often buried below layers of insulator and conductors. Once the ROI is identified, the circuit can be “deprocessed,” that is, overlying structures can be removed, to expose the ROI. Current deprocessing techniques typically provide access to the structure in a planar fashion—ion beam milling creates surfaces orthogonal to the device surface in order to allow imaging, probing, or other localization techniques. Likewise cleaving the wafer or parallel-lapping deprocessing provides access to a plane of the structure.
Techniques to analyze the ROI include, for example, micro-probing, in which conductive probes are contacted to the conductors on the IC to apply and/or measure voltages or currents. Another technique for analyzing a ROI is voltage contrast imaging, in which a charged particle beam image, which is sensitive to any voltage on the imaged surface, is obtained while a voltage is applied to a part of the circuit. Other analysis techniques include scanning probe microscopy, such as scanning-capacitance microscopy, in which a fine probe is scanned above the region of interest and the electrical or physical behavior of the probe is monitored. As used herein, analysis techniques include imaging techniques.
Current techniques map locations on an integrated circuit as if the device were a city in which buildings have only one floor—simply getting the street address is sufficient to deliver the mail to the correct location. Emerging three dimensional (3D) IC fabrication technologies do not constrain the active area (i.e., transistor or memory cell) to one plane in the Z direction—active areas occupy many levels of 3D devices. The city map is now populated by skyscrapers—the address information needs to reference to which floor the mail is to be delivered. Rather than identify a 2D region of interest, an engineer will require distinct isolation of a volume-of-interest (VOI) in three dimensions.
For 3D IC structures, prior art techniques that provide planar access are inherently limited to two dimensions of the structure, resulting in either more complicated or impossible final access to the VOI.